1. Field of the Invention
The present invention relates to Peripheral Component Interconnect (PCI) interfaces and, more particularly, to a PCI host bridge that uses PCI-X Mode 2 ECC pin connections as Grant/Request pin connections when a device is not operating in PCI-X Mode 2.
2. Background Art
Peripheral Component Interconnect (PCI) interfaces have been used to provide high-speed connectivity between devices in a multi-device system, for example, a processor based system such as a personal computer.
FIG. 1 is a diagram illustrating a conventional implementation of a PCI bus system architecture 100. The system 100 includes a processor 102 coupled to a memory controller 104 via a local bus 106′. The processor 102 and the memory controller 104 are coupled to a PCI local bus 106 (labeled PCI Local Bus #0) via a host bridge 108.
The host bridge 108 provides a low latency path through which the processor 102 may directly access PCI devices 110, for example a network interface card 110a providing access to a local area network 112, a disc drive (SCSI) controller 110b providing access to disk drives 114, an audio card 110c, a motion picture card 110d, or a graphics card 110e configured for driving a monitor 116. The host bridge 108 also provides a high bandwidth path allowing PCI masters on the PCI bus 106 direct access to the system memory 118 via the memory controller 104. A cache memory 120 is independent of the system memory 118 for use by the processor 102.
The term “host bridge” refers to the bridge device 108 that provides access to the system memory 118 for the devices 110 connected to the PCI bus 106. A PCI-to-PCI bridge 122 also may be used to connect a second PCI bus 124 to the PCI bus 106, the second PCI bus 124 configured for connecting other I/O devices 126.
Newer PCI bus protocols are being published, including PCI-X Mode 2, that provide enhanced PCI functionality. These newer PCI bus protocols include the PCI Local Bus Specification, Rev 2.3, the PCI-X Protocol Addendum to the PCI Local Bus Specification, Rev. 2.0a, and the PCI-to-PCI Bridge Architecture Specification, Rev 1.2.
The newer PCI host bridge devices may utilize HyperTransport™ technology, which specifies a data rate of 1.6 GHz between each differential signal pair. Hence, the newer PCI bus devices need to be implemented using newer semiconductor fabrication process technology to optimize the higher speed requirements of HyperTransport™ technology.
In normal PCI mode, up to five devices can be supported by the PCI host bridge device. Each device must have two pins, one pin for a Grant (GNT) signal and another pin for a Request (REQ) signal to use the PCI bus. Thus a total of ten pin connections are needed on the PCI host bridge device.
The PCI-X Protocol Addendum Rev 2.0a defines four error correcting code (ECC) signals for use in PCI-X Mode 2. Thus, four pin connections must be added to PCI/PCI-X host bridge device. Only one external device can be supported with ECC in PCI-X Mode 2.